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d a t a sh eet preliminary speci?cation file under integrated circuits, ic22 may 1993 integrated circuits SAA7186 digital video scaler
may 1993 2 philips semiconductors preliminary speci?cation digital video scaler SAA7186 contents 1 features 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning 7 functional description 8 operation cycle 9i 2 c-bus format 10 limiting values 11 dc characteristics 12 ac characteristics 13 processing delays 14 programming example 15 package outline 16 soldering 17 definitions 18 life support applications 19 purchase of philips i 2 c components
may 1993 3 philips semiconductors preliminary speci?cation digital video scaler SAA7186 1 features scaling of video picture windows down to randomly sized windows processes maximum 1023 pixels per line and 1023 lines per field two-dimensional data processing for improved signal quality of scaled video data and for compression of video data 16-bit yuv input data buffer interlace/non-interlace video data processing and field control line memories in y path and uv path to store two lines, each with 2 768 8 bit capacity vertical sync processing by scale control non-scaled mode to get full picture or to gate videotext lines uv input and output data binary/twos complement switchable rgb matrix and anti-gamma roms 16-word fifo register for 32-bit output data output formats: 5-bit and 8-bit rgb, 8-bit yuv or 8-bit monochrome 2 general description the cmos circuit SAA7186 scales and filters digital video data to randomly sized picture windows. yuv input data in 4:2:2 format are required (saa7191b source). 3 quick reference data 4 ordering information symbol parameter min. typ. max. unit v dd supply voltage 4.5 5 5.5 v i dd tot total supply current (inputs low, without output load) - - 180 ma v i data input level ttl-compatible v o data output level ttl-compatible llc input clock frequency - - 32 mhz t amb operating ambient temperature range 0 - 70 c extended type number package pins pin position material code SAA7186 100 qfp plastic sot317-2
may 1993 4 philips semiconductors preliminary speci?cation digital video scaler SAA7186 5 block diagram handbook, full pagewidth SAA7186 scale control i c control vertical filter interpolator v ss1 v dd1 vro (31 to 0); 49 meh422-1 fig.1 block diagram. input data buffer 20 to 17 luminance decimation filter chroma decimation filter arithmetic line memory (2x8x768) vertical filter arithmetic line memory (2x8x768) rgb matrix followed by anti-gamma roms chroma keyer output formatter output fifo register 2 clock generation 36 35 46 44 45 sda scl iicsa cref (1) without pins 60, 72, 84 and 96, these pins are not connected resn uvin (7-0) yin (7-0) 13 to 10 25 to 22 33 to 30 y uv y u v u v 8 8 15 8 48 47 50 51 vlck voen btst incadr hfl +5 v 5, 14, 26,40, 55, 67, 76, 91 to v dd8 7 8 sp ap 3, 16, 28, 42, 53, 65, 78, 89 i.c. 4, 6, to v ss8 43 href vs 37 38 32-bit vram port output rgb or yuv n.c. 9, 15, 21, 27, 29, 39, 34, 41, 52, 54, 60, 66, 72, 79, 84, 90, 96 output pins (1): 56 to 64 68 to 75, 77 80 to 88 92 to 100 controls status lnq hrefd 1 2 llc fig.1 block diagram.
may 1993 5 philips semiconductors preliminary speci?cation digital video scaler SAA7186 6 pinning symbol pin status description lnq 1 o line quali?er signal; active polarity de?ned by qpl-bit in 10 (vclk strobed) hrefd 2 o delay-compensated href output signal (vclk strobed) v ss1 3 - gnd1 (0 v) i.c. 4 - internally connected v dd1 5 - +5 v supply voltage 1 i.c. 6 - internally connected sp 7 i connected to ground (shift pin for testing) ap 8 i connected to ground (action pin for testing) n.c. 9 - not connected uvin0 10 i time-multiplexed colour-difference input data (bits 0 to 3) uvin1 11 i uvin2 12 i uvin3 13 i v dd2 14 - +5 v supply voltage 2 n.c. 15 - not connected v ss2 16 - gnd2 (0 v) uvin4 17 i time-multiplexed colour-difference input data (bits 4 to 7) uvin5 18 i uvin6 19 i uvin7 20 i n.c. 21 - not connected yin0 22 i luminance input data (bits 0 to 3) yin1 23 i yin2 24 i yin3 25 i v dd3 26 - +5 v supply voltage 3 n.c. 27 - not connected v ss3 28 - gnd3 (0 v) n.c. 29 - not connected yin4 30 i luminance input data (bits 4 to 7) yin5 31 i yin6 32 i yin7 33 i n.c. 34 - not connected cref 35 i clock reference, external sync signal llc 36 i line-locked system clock input signal (twice of pixel rate) href 37 i horizontal reference, pixel data clock signal (also present during vertical blanking) vs 38 i vertical sync input signal (approximately 6 lines long) n.c. 39 - not connected v dd4 40 - +5 v supply voltage 4
may 1993 6 philips semiconductors preliminary speci?cation digital video scaler SAA7186 n.c. 41 - not connected v ss4 42 - gnd4 (0 v) resn 43 i reset input (active-low for at least 30llc periods) sda 44 i/o iic-bus data line scl 45 i iic-bus clock line iicsa 46 i set module address input of iic-bus (low = b8, high = bc) btst 47 i output disable input; high sets all data outputs to high-impedance state incadr 48 o line increment / vertical reset control output line hfl 49 o fifo register half-full ?ag output voen 50 i vram port output enable input (active-low) vclk 51 i fifo register clock input signal n.c. 52 - not connected v ss5 53 - gnd5 (0 v) n.c. 54 - not connected v dd5 55 - +5 v supply voltage 5 vro31 56 o video output; 32-bit vram output port (bits 31 to 28) vro30 57 o vro29 58 o vro28 59 o n.c. 60 - not connected vro27 61 o video output; 32-bit vram output port (bits 27 to 24) vro26 62 o vro25 63 o vro24 64 o v ss6 65 - gnd6 (0 v) n.c. 66 - not connected v dd6 67 - +5 v supply voltage 6 vro23 68 o video output; 32-bit vram output port (bits 23 to 22) vro22 69 o vro21 70 o video output; 32-bit vram output port (bits 21 to 20) vro20 71 o n.c. 72 - not connected vro19 73 o video output; 32-bit vram output port (bits 19 to 17) vro18 74 o vro17 75 o v dd7 76 - +5 v supply voltage 7 vro16 77 o video output; 32-bit vram output port (bit16) v ss7 78 - gnd7 (0 v) n.c. 79 - not connected symbol pin status description
may 1993 7 philips semiconductors preliminary speci?cation digital video scaler SAA7186 vro15 80 o video output; 32-bit vram output port (bits 15 to 12) vro14 81 o vro13 82 o vro12 83 o n.c. 84 - not connected vro11 85 o video output; 32-bit vram output port (bits 11 to 8) vro10 86 o vro9 87 o vro8 88 o v ss8 89 o gnd8 (0 v) n.c. 90 - not connected v dd8 91 - +5 v supply voltage 8 vro7 92 o video output; 32-bit vram output port (bits 7 to 4) vro6 93 o vro5 94 o vro4 95 o n.c. 96 - not connected vro3 97 o video output; 32-bit vram output port (bits 3 to 0) vro2 98 o vro1 99 o vro0 100 o symbol pin status description
may 1993 8 philips semiconductors preliminary speci?cation digital video scaler SAA7186 6.1 pin con?guration fig.2 pin configuration. handbook, full pagewidth SAA7186 87 82 83 84 85 86 2 4 1 3 95 96 97 98 99 94 89 90 91 92 93 88 meh421 6 5 7 lnq ss1 8 9 10 11 12 17 16 15 14 13 18 19 81 100 hrefd. i.c. v i.c. dd2 v ss2 v dd1 v sp. ap uvin0 n.c. uvin1 uvin2 uvin3 n.c. uvin4 uvin5 uvin6 20 uvin7 21 22 23 24 25 n.c. yin0 yin2 yin3 yin1 44 39 43 42 41 40 45 50 49 48 47 46 31 32 37 36 35 34 33 38 v yin5 yin6 yin7 cref llc href vs n.c. n.c. dd4 v ss4 n.c. resn sda scl iicsa btst incadr hfl voen v dd8 n.c. v ss8 n.c. vro0 n.c. vro1 vro2 vro3 vro4 vro5 vro6 vro7 vro8 vro9 vro10 vro11 vro12 vro13 vro14 26 27 28 29 30 n.c. yin4 ss3 v dd3 v n.c. 52 53 54 55 56 57 58 59 60 61 62 63 51 68 69 70 64 65 66 67 ss6 dd6 v 76 77 78 79 80 vro15 vro16 n.c. vro21 vro22 vro23 n.c. vro24 vro25 vro26 vro27 n.c. v vro28 vro29 vro30 vro31 n.c. dd5 v ss5 v n.c. vclk 71 72 73 74 75 vro17 vro18 vro19 n.c. vro20 dd7 v ss7 v
may 1993 9 philips semiconductors preliminary speci?cation digital video scaler SAA7186 7 functional description the input port is output of philips digital video multistandard decoders (saa7151b, saa7191b) or other similar sources. the SAA7186 input supports the 16-bit yuv 4:2:2 format. the video data from the input port are converted into a unique internal twos complement data stream and are processed in horizontal direction in two separate decimation filters. then they are processed in vertical direction by the vertical processing unit (vpu). chrominance data are interpolated to a 4:4:4 format; a chroma keying bit is generated. the 4:4:4 yuv data are then converted from the yuv to the rgb domain in a digital matrix. rom tables in the rgb data path can be used for anti-gamma correction of gamma-corrected input signals. uncorrected rgb and yuv signals can be bypassed. a scale control unit generates reference and gate signals for scaling of the processed video data. after data formatting to the various vram port formats, the scaled video data are buffered in the 16 word 32-bit output fifo register. the fifo output is directly connected to the vram output bus vro(31-0). specific reference signals support an easy memory interfacing. all functions of the SAA7186 are controlled via i 2 c-bus using 17 subaddresses. the external microcontroller can get information by reading the status register. 7.1 video input port the 16-bit yuv input data in 4:2:2 format (table 1) consist of 8-bit luminance data y (pins yin(7-0)) and 8-bit time-multiplexed colour-difference data uv (pins uvin(7-0)). the input data are clocked in by the signals llc and cref (fig.3). href and vs inputs define the video scan pattern (window). sequential input data are limited to maximum 768 active pixels per line if the vertical filter is active uv can be processed in straight binary and twos complement representation (controlled by tcc) 7.2 decimation ?lters the decimation filters perform accurate horizontal filtering of the input data stream. signal characteristics are matched in front of the pixel decimation stage, thus disturbing artifacts, caused by the pixel dropping, are reduced. the signal bandwidth can be reduced in steps of: 2-tap filter = - 6 db at 0.325 pixel rate 3-tap filter = - 6 db at 0.25 pixel rate 4-tap filter = - 6 db at 0.21 pixel rate 5-tap filter = - 6 db at 0.125 pixel rate 9-tap filter = - 6 db at 0.075 pixel rate the different characteristics are chosen dependent on the defined scaling parameters in an adaptive filter mode (afs-bit = 1). the filter characteristics can also be selected independently by control bits hf2 to hf0 at afs-bit = 0. 7.3 vertical ?lters y and uv data are handled in separate filters (fig.1). each of the two line memories has a capacity of 2 768 8-bit. thus two complete video lines of 4:2:2 yuv data can be stored. the vpu is split into two memory banks and one arithmetic unit. the available processing modes, respectively transfer functions, are selectable by the bits vp1 and vp0 if afs = 0. an adaptive mode is selected by afs = 1. disturbing artifacts, generated by line dropping, are reduced. adaptive ?lter selection (afs = 1): scaling ratio filter function (refer to i 2 c section) xd/xs horizontal 1 14/15 11/15 7/15 3/15 bypassed ?lter 1 ?lter 6 ?lter 3 ?lter 4 yd/ys vertical 1 13/15 4/15 bypassed ?lter 1 ?lter 2
may 1993 10 philips semiconductors preliminary speci?cation digital video scaler SAA7186 7.4 rgb matrix y data and uv data are converted after interpolation into rgb data according to ccir601 recommendation. data are bypassed in yuv or monochrome modes. table 1 4 : 2 : 2 format (pixels per line). the time frames are controlled by the href signal. note 1. e = even pixel; o = odd pixel the matrix equations are these considering the digital quantization: r=y + 1.375 v g=y - 0.703125 v - 0.34375 u b=y + 1.734375 u. anti-gamma rom tables: rom tables are implemented at the matrix output to provide anti-gamma correction of the rgb data. a curve for a gamma of 1.4 is implemented the tables can be used (rtb-bit = 0) to compensate gamma correction for linear data representation of rgb output data. input pixel byte sequence yin7 yin6 yin5 yin4 yin3 yin2 yin1 yin0 ye7 ye6 ye5 ye4 ye3 ye2 ye1 ye0 yo7 yo6 yo5 yo4 yo3 yo2 yo1 yo0 ye7 ye6 ye5 ye4 ye3 ye2 ye1 ye0 yo7 yo6 yo5 yo4 yo3 yo2 yo1 yo0 ye7 ye6 ye5 ye4 ye3 ye2 ye1 ye0 uvin7 uvin6 uvin5 uvin4 uvin3 uvin2 uvin1 uvin0 ue7 ue6 ue5 ue4 ue3 ue2 ue1 ue0 ve7 ve6 ve5 ve4 ve3 ve2 ve1 ve0 ue7 ue6 ue5 ue4 ue3 ue2 ue1 ue0 ve7 ve6 ve5 ve4 ve3 ve2 ve1 ve0 ue7 ue6 ue5 ue4 ue3 ue2 ue1 ue0 y frame 0 1 2 3 4 uv frame 0 2 4 7.5 chrominance signal keyer the keyer generates an alpha signal to achieve a 5-5-5 +a rgb alpha output signal. therefore, the processed uv data amplitudes are compared with thresholds set via i 2 c-bus (subaddresses 0c to 0f). a logical 1 signal is generated if the amplitude is inside the specified amplitude range, otherwise a logical 0 is generated. keying can be switched off by setting the lower limit higher than the upper limit (0c or 0e and 0d or 0f). 7.6 scale control and vertical regions the scale control block sc includes vertical address/sequence counters to define the current position in the input field and to address the internal vpu memories. to perform scaling, xd of xs pixel selection in horizontal direction and yd of ys line selection in vertical direction are applied. the pixel and line dropping are controlled at the input of the fifo register. to control the decimation filter function and the vertical data processing in the adaptive mode (afs = 1), the scaling ratio in horizontal and vertical direction is estimated in the sc block. the input field can be divided into two vertical regions - the bypass region and the scaling region, which are defined via i 2 c-bus by the parameters vs, vc, yo and ys. vertical bypass region: data are not scaled and independent of i 2 c-bits fs1, fs0 the output format is always 8-bit greyscale (monochrome). the SAA7186 outputs all active pixels of a line, defined by the href input signal if the vertical bypass region is active. this can be used, for example, to store videotext information in the field memory. the start line of the bypass region is defined by vs; the number of lines to be bypassed is defined by vc. vertical scaling region: data is scaled with start at line yo and the output format is selected when fs1, fs0 are valid. this is the normal operation area. the input/output screen dimensions in horizontal and vertical direction are defined by the parameters xo, xs and xd for horizontal yo, ys and yd for vertical. the circuit processes xs samples of a line. remaining pixels are ignored if a line is longer than xs. if a line is
may 1993 11 philips semiconductors preliminary speci?cation digital video scaler SAA7186 shorter than xs, processing is aborted when the falling edge of href is detected. vertical regions in fig.4: the two regions can be programmed via i 2 c-bus, whereby regions should not overlap (active region overrides the bypass region). the start of a normal active picture depends on video standard and has to be programmed to the correct value. the offsets xo and yo have to be set according to the internal processing delays to ensure the complete number of destination pixels and lines (table 6). the scaling parameters can be used to perform a panning function over the video frame/field. fig.3 horizontal and data multiplex timing. handbook, full pagewidth llc cref href end of active line byte number for pixels: y signal u and v signal n ?5 vn-5 n ?4 un-3 n ?3 vn-3 n ?2 un-1 n ?1 vn-1 n un-5 meh410 handbook, full pagewidth llc cref href start of active line 0 u0 1 v0 2 u2 3 v2 4 u4 5 v4 6 u6 7 v6 y signal u and v signal byte numbers for pixles: meh411
may 1993 12 philips semiconductors preliminary speci?cation digital video scaler SAA7186 7.7 output data representation and levels output data representation of the yuv data can be modified by bit mct (subaddress 10). the dc gain is 1 for yuv input data. the corresponding rgb levels are defined by the matrix equations. the luminance levels are limited according to ccir 601 16 (239) = black 235 (20) = white (..) = greyscale luminance levels if the yuv or monochrome luminance output formats are selected. the signal levels of the rgb formats are limited in 8-bit to 0 or 255. for the 5-bit rgb formats a truncation from 8-bit to 5-bit is implemented. fill values are inserted dependent on longword position and destination size: 0 in rgb formats and for y twos complement u, v 128 for u, v (straight binary) 255 in 8-bit greyscale format the unused output values of the yuv and greyscale formats can be used for other purposes. fig.4 vertical regions. handbook, full pagewidth meh357-1 scaling region vertical bypass start first valid line bypass region vertical blanking vertical sync scaling region start vs vertical bypass count equals vs yo scaling region count equals ys y-size source
may 1993 13 philips semiconductors preliminary speci?cation digital video scaler SAA7186 table 2 vram port output data formats at efe-bit = 0 dependent on fs1 and fs0 bits (set via i 2 c-bus) note 1. a = keying bit; r, g, b, y, u and v = digital signals; e = even pixel number; o = odd pixel number; a b c d = consecutive pixels pixel output bits fs1 = 0; fs0 = 0 rgb 5-5-5 + 1 32-bit words fs1 = 0; fs0 = 1 yuv 4:2:2 32-bit words fs1 = 1; fs0 = 0 yuv 4:2:2 test 16-bit words fs1 = 1; fs0 = 1 8-bit monochrome 32-bit words pixel order n n + 2n + 4n n + 2n + 4n n + 1n + 2 n n + 1 n + 4 n + 5 n + 8 n + 9 vro31 vro30 vro29 vro28 a r4 r3 r2 a r4 r3 r2 a r4 r3 r2 ye7 ye6 ye5 ye4 ye7 ye6 ye5 ye4 ye7 ye6 ye5 ye4 ye7 ye6 ye5 ye4 yo7 yo6 yo5 yo4 ye7 ye6 ye5 ye4 ya7 ya6 ya5 ya4 ya7 ya6 ya5 ya4 ya7 ya6 ya5 ya4 vro27 vro26 vro25 vro24 r1 r0 g4 g3 r1 r0 g4 g3 r1 r0 g4 g3 ye3 ye2 ye1 ye0 ye3 ye2 ye1 ye0 ye3 ye2 ye1 ye0 ye3 ye2 ye1 ye0 yo3 yo2 yo1 yo0 ye3 ye2 ye1 ye0 ya3 ya2 ya1 ya0 ya3 ya2 ya1 ya0 ya3 ya2 ya1 ya0 vro23 vro22 vro21 vro20 g2 g1 g0 b4 g2 g1 g0 b4 g2 g1 g0 b4 ue7 ue6 ue5 ue4 ue7 ue6 ue5 ue4 ue7 ue6 ue5 ue4 ue7 ue6 ue5 ue4 ve7 ve6 ve5 ve4 ue7 ue6 ue5 ue4 yb7 yb6 yb5 yb4 yb7 yb6 yb5 yb4 yb7 yb6 yb5 yb4 vro19 vro18 vro17 vro16 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 ue3 ue2 ue1 ue0 ue3 ue2 ue1 ue0 ue3 ue2 ue1 ue0 ue3 ue2 ue1 ue0 ve3 ve2 ve1 ve0 ue3 ue2 ue1 ue0 yb3 yb2 yb1 yb0 yb3 yb2 yb1 yb0 yb3 yb2 yb1 yb0 pixel order n + 1n + 3n + 5n + 1n + 3n + 5 outputs not used n + 2 n + 3 n + 6 n + 7 n + 10 n + 11 vro15 vro14 vro13 vro12 a r4 r3 r2 a r4 r3 r2 a r4 r3 r2 yo7 yo6 yo5 yo4 yo7 yo6 yo5 yo4 yo7 yo6 yo5 yo4 x x x x x x x x x x x x yc7 yc6 yc5 yc4 yc7 yc6 yc5 yc4 yc7 yc6 yc5 yc4 vro11 vro10 vro9 vro8 r1 r0 g4 g3 r1 r0 g4 g3 r1 r0 g4 g3 yo3 yo2 yo1 yo0 yo3 yo2 yo1 yo0 yo3 yo2 yo1 yo0 x x x x x x x x x x x x yc3 yc2 yc1 yc0 yc3 yc2 yc1 yc0 yc3 yc2 yc1 yc0 vro7 vro6 vro5 vro4 g2 g1 g0 b4 g2 g1 g0 b4 g2 g1 g0 b4 ve7 ve6 ve5 ve4 ve7 ve6 ve5 ve4 ve7 ve6 ve5 ve4 x x x x x x x x x x x x yd7 yd6 yd5 yd4 yd7 yd6 yd5 yd4 yd7 yd6 yd5 yd4 vro3 vro2 vro1 vro0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 ve3 ve2 ve1 ve0 ve3 ve2 ve1 ve0 ve3 ve2 ve1 ve0 x x x x x x x x x x x x yd3 yd2 yd1 yd0 yd3 yd2 yd1 yd0 yd3 yd2 yd1 yd0
may 1993 14 philips semiconductors preliminary speci?cation digital video scaler SAA7186 table 3 vram port output data formats at efe-bit = 1 dependent on fs1 and fs0 bits (set via i 2 c-bus) notes 1. a = keying bit; r, g, b, y, u and v = digital signals; e = even pixel number; o = odd pixel number; a b c d = consecutive pixels; o/e = odd/even flag 2. yuv 16-bit format: the keying signal a is defined only for yu time steps. the corresponding yv sample has also to be keyed. the a signal in monochrome mode can be used only in the transparent mode (ttr = 1), in this case ya = yb. 3. data valid only when transparent mode active (ttr-bit = 1) and vclk pin connected to llc/2 clock rate. pixel output bits fs1 = 0; fs0 = 0 rgb 5-5-5 + 1 16-bit words fs1 = 0; fs0 = 1 yuv 4:2:2 16-bit words fs1 = 1; fs0 = 0 rgb 8-8-8 24-bit words fs1 = 1; fs0 = 1 8-bit monochrome 16-bit words pixel order n n + 1n + 2n n + 1n + 2n n + 1n + 2 n n + 1 n + 2 n + 3 n + 4 n + 5 vro31 vro30 vro29 vro28 a r4 r3 r2 a r4 r3 r2 a r4 r3 r2 ye7 ye6 ye5 ye4 yo7 yo6 yo5 yo4 ye7 ye6 ye5 ye4 r7 r6 r5 r4 r7 r6 r5 r4 r7 r6 r5 r4 ya7 ya6 ya5 ya4 ya7 ya6 ya5 ya4 ya7 ya6 ya5 ya4 vro27 vro26 vro25 vro24 r1 r0 g4 g3 r1 r0 g4 g3 r1 r0 g4 g3 ye3 ye2 ye1 ye0 yo3 yo2 yo1 yo0 ye3 ye2 ye1 ye0 r3 r2 r1 r0 r3 r2 r1 r0 r3 r2 r1 r0 ya3 ya2 ya1 ya0 ya3 ya2 ya1 ya0 ya3 ya2 ya1 ya0 vro23 vro22 vro21 vro20 g2 g1 g0 b4 g2 g1 g0 b4 g2 g1 g0 b4 ue7 ue6 ue5 ue4 ve7 ve6 ve5 ve4 ue7 ue6 ue5 ue4 g7 g6 g5 g4 g7 g6 g5 g4 g7 g6 g5 g4 yb7 yb6 yb5 yb4 yb7 yb6 yb5 yb4 yb7 yb6 yb5 yb4 vro19 vro18 vro17 vro16 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 ue3 ue2 ue1 ue0 ve3 ve2 ve1 ve0 ue3 ue2 ue1 ue0 g3 g2 g1 g0 g3 g2 g1 g0 g3 g2 g1 g0 yb3 yb2 yb1 yb0 yb3 yb2 yb1 yb0 yb3 yb2 yb1 yb0 pixel order n n + 1n + 2n n + 1n + 2n n + 1n + 2 n n + 1 n + 2 n + 3 n + 4 n + 5 vro15 vro14 vro13 vro12 x x x x x x x x x x x x x x x x x x x x x x x x b7 b6 b5 b4 b7 b6 b5 b4 b7 b6 b5 b4 x x x x x x x x x x x x vro11 vro10 vro9 vro8 x x x x x x x x x x x x x x x x x x x x x x x x b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 x x x x x x x x x x x x vro7 (2, 3) vro6 (3) vro5 (3) vro4 (3) a o/e vgt hgt a o/e vgt hgt a o/e vgt hgt a o/e vgt hgt x o/e vgt hgt a o/e vgt hgt a o/e vgt hgt a o/e vgt hgt a o/e vgt hgt a o/e vgt hgt a o/e vgt hgt a o/e vgt hgt vro3 vro2 (3) vro1 (3) vro0 (3) x hrf lnq pxq x hrf lnq pxq x hrf lnq pxq x hrf lnq pxq x hrf lnq pxq x hrf lnq pxq x hrf lnq pxq x hrf lnq pxq x hrf lnq pxq x hrf lnq pxq x hrf lnq pxq x hrf lnq pxq
may 1993 15 philips semiconductors preliminary speci?cation digital video scaler SAA7186 7.8 output fifo register and vram output port the output fifo register is the buffer between the video data stream and the vram data input port. resized video data are buffered and formatted. 32-, 24- and 16-bit video data modes are supported. the various formats are selected by the bits efe, fs1 and fs0. vram port formats are shown in tables 2 and 3. the fifo register capacity is 16 word 32 bit (for 32-, 24-, or 16-bit video data). the bits lw1 and lw0 can be used to define the position of the first pixel each line in the 32-bit longword formats or to shift the uv sequence to vu in the 16-bit yuv formats (lw1 = 1). vram port inputs are: vclk to clock the fifo register output data and voen to enable output data. vram port outputs are: the hfl flag (half-full flag), the signal incadr (refer to section data burst transfer) and the reference signals for pixel and line selection on outputs vro(7-0) (only for 24- and 16-bit video data formats refer to transparent data transfer). 7.9 vram port transfer procedures data transfer on the vram port can be done asynchronously controlled by outputs hfl, incadr and input vclk (data burst transfer with bit ttr = 0). data transfer on the vram port can be done synchronously controlled by output reference signals on outputs vro(7-0) and a clock rate of llc/2 on input vclk (transparent data transfer with bit ttr = 1 and efe = 1). the scaling capability of the SAA7186 can be used in various applications. 7.10 data burst transfer mode data transfer on the vram port is asynchronously (ttr = 0). this mode can be used for all output formats. four signals for communication with the external memory are provided. hfl flag, the half-full flag of the fifo output register is raised when the fifo contains at least 8 data words (hfl = high). by setting hfl = 1, the SAA7186 requests a data burst transfer by the external memory controller, that has to start a transfer cycle within the next 32 llc cycles for 32-bit longword modes (16 llc cycles for 16- and 24-bit modes). if there are pixels in the fifo at the end of a line, which are not transferred, the circuit fills up the fifo register with fill pixels until it is half-full and sets the hfl flag to request a data burst transfer. after transfer is done, hfl is used in combination with incadr to indicate the line increments (figures 6 and 7). incadr output signal is used in combination with hfl to control horizontal and vertical address generation for a memory controller. the pulse sequence depends on field formats (interlace/ non-interlace or odd/even fields, figures 6 and 7) and control bits of (subaddress 00). hfl = 1 at the rising edge of incadr: the end of line is reached, request for line address increment hfl = 0 at the rising edge of incadr: the end of field/frame is reached, request for line and pixel addresses reset (the distance from the last half-full request hfl to the incadr pulse may be longer than 64 llc. the hfl state is defined for minimum 4 llc in front of the rising edge of incadr and minimum 2 llc afterwards.) vclk input signal to clock the fifo register output data vro(n). new data are placed on the vro(n) port with the rising edge of vclk (fig.5). voen input enables output data vro(n). the outputs are in 3-state mode at voen = high. voen changes only when vclk is low. if vclk pulses are applied during voen = high, the outputs remain inactive, but the fifo register accepts the pulses. 7.11 transparent data transfer mode data transfer on the vram port can be achieved synchronously (ttr = 1). with a continuous clock rate of llc/2 on input vclk, the SAA7186 delivers a continuously processed data stream. therefore, the extended formats of the vram output port have to be selected (bit efe = 1; table 3). the reference and gate signals on outputs vro(6-1) and the lnq signal are delivered in each field (means scaled and ignored fields). the pxo signal (also vro0) is only delivered in active fields. the output signals vro(7-0) can be used to buffer qualified pre-processed rgb or yuv video data (notice: the yuv data are only valid in qualified time slots). control output signals in table 3 are:
may 1993 16 philips semiconductors preliminary speci?cation digital video scaler SAA7186 7.12 power-on reset the fifo register contents are undefined outputs vro are set to high-impedance state output incadr = high output hfl = low until the vpe bit is set to 1 subaddress 10 is set to 00h and vpe-bit in subaddress 00 is set to zero (table 4). a keying signal of the chroma keyer o/e odd/even ?eld bit according to the internal ?eld processing vgt vertical gate signal, 1 marks the scaling window in vertical direction from yo to (yo + ys) lines, cut by vs. hgt horizontal gate signal, 1 marks horizontal direction from xo to (xo + xs) lines, cut by href. hrf delay compensated horizontal reference signal. lnq line quali?er signal, active polarity is de?ned by qpl bit. pxq pixel quali?er signal, active polarity is de?ned by qpp bit.
may 1993 17 philips semiconductors preliminary speci?cation digital video scaler SAA7186 fig.5 output port transfer to vram at 32-bit data format without scaling. if vclk cycles occur at voen = high, the fifo register is unchanged, but the outputs vro(31-0) remain in 3-state position. handbook, full pagewidth meh407 pixclk (llc/2) fifo memory filling level 6787 7 65 5 4 33 7 1 2 3 4 5 6 0 7 hfl vclk voen vro(n) min. 8 samples available in fifo max. 32llc (16 pixclk 1 transfer cycle (8 vclk cycles) fig.6 vertical reset timing to the vram. handbook, full pagewidth meh406 min. 64llc min. set-up time vertical blanking active video 64llc 10llc line n line n+1 (1) (1) pulse only at interlace scan line increment (vram) only in odd field (1) internal signal hfl incadr last half-full request for line n vertical reset
may 1993 18 philips semiconductors preliminary speci?cation digital video scaler SAA7186 fig.7 horizontal increment timing to the vram. handbook, full pagewidth meh405-1 min. 64llc min. set-up time horizontal blanking active video active video 64llc 2llc 6llc 6llc 10llc line n line n+1 (1) (1) pulse only at interlace scan line increment (vram) (1) internal signal hfl incadr last half-full request for line n first half-full request for line n+1 fig.8 reference signals for scaling window.
may 1993 19 philips semiconductors preliminary speci?cation digital video scaler SAA7186 7.13 field processing the phase of the field sequence (odd/even dependent on inputs href and vs) is detected by means of the falling edge of vs. the current field phase is reported in the status byte by the oef bit (table 5). oef bit can be stable 0 or 1 for non-interlaced input frames or non standard input signals vs and/or href (nominal condition for vs and href - saa7191 b with active vertical noise limiter). a free-running odd/even flag is generated for internal field processing if the detection reports a stable oef bit. the poe bit (subaddress 0b) can be used to change the polarity of the internal flag (in case of non-standard vs and href signals) to control the phase of the free-running flag, and to compensate mis-detections. thus, the SAA7186 can be used under various vs/href timing conditions. the SAA7186 operates on fields. to support progressive displays and to avoid movement blurring and artifacts, the circuit can process both or single fields of interlaced or non-interlaced input data. therefore the of bits can be used. the bits of1 and of0 (table 6) determine the incadr/hfl generation in data burst transfer mode. one of the fields (odd or even) is ignored when of1 = 1; then no line increment sequence (incadr/hfl) is generated, the vertical reset pulse is only generated. with of1 = of0 = 0 the circuit supports correct interlaced data storage. two incadr/hfl sequences are generated in each qualified line; additionally an incadr/hfl sequence after the vertical reset sequence of an odd field is generated. thereby, the scaled lines are automatically stored in the right sequence. 8 operation cycle the operation is synchronized by the input field. the cycle is specified in the flow chart (fig.9). the circuit is inactive after power-on reset, vpo is 0 and the fifo control is set empty. the internal control registers are updated with the falling edge of vs signal. the circuit is switched active and waits for a transmission of vs and a vertical reset sequence to the memory controller. afterwards, the circuit waits for the beginning of a scaling or bypass region. the processing of a current line is finished when a vertical sync pulse appears. the circuit performs a coefficient update and generates a new vertical reset (if it is still active). line processing starts when a line is decided to be active, the circuit starts to scale it. active pixels are loaded into the fifo register. an hfl flag is generated to initialize a data transfer when eight words are completed. the line end is reached when the programmed pixel number is processed or when a horizontal sync pulse occurs. if there are pixels in the fifo register, it is filled up until it is half-full to cause a data transfer. horizontal increment pulses are transmitted after this data transfer. remarks: the SAA7186 will always wait for the href/vs pulse before the line increment/vertical reset sequence is performed. after each line/field, the fifo control is set to empty when incadr/hfl sequence is transmitted. no additional actions are necessary if the memory controller has ignored the hfl signal. there is no need to handle overflow/underflow of the fifo register.
may 1993 20 philips semiconductors preliminary speci?cation digital video scaler SAA7186 fig.9 operation cycle handbook, full pagewidth mgl119 external reset, vpe = 0 vertical sync detected ? coefficient update do vertical reset yes yes yes yes no no no no no process a line set bypass mode in control stage set scaling active in control stage yes vertical sync detected ? current line in active region ? current line in bypass region ? vpe = 1 ?
may 1993 21 philips semiconductors preliminary speci?cation digital video scaler SAA7186 fig.10 SAA7186 system configuration in data burst transfer mode (ttr = , vclk = continuous). handbook, full pagewidth meh554 adc tda8708a dmsd saa7151b/91b dvs SAA7186 ram video graphics scgc saa7157/97 cpu system ram memory controller buffer data bus address / control bus system clock vclk voen hfl incadr rgb/yuv display data address control yuv format 4.2:2 llc / cref lfco cvbs cvbs digital href / vs fig.11 SAA7186 system configuration in transparent data transfer mode (ttr = 1, efe = 1, vclk = continuous (_llc2)). handbook, full pagewidth meh555 adc tda8708a dmsd saa7151b/91b dvs SAA7186 ram video graphics scgc saa7157/97 memory controller rgb/yuv display data address write yuv format 4.2:2 llc / cref lfco cvbs cvbs digital href / vs fifo buffer (vro(31-8)) inv llc2 vclk = llc2 voen = 1 qualifier and references (vro(7-0)) control read
may 1993 22 philips semiconductors preliminary speci?cation digital video scaler SAA7186 fig.12 vs timing for video input source saa7191b. handbook, full pagewidth (a) 1st field meh412 input cvbs href vs 625123456789 541 x 2/llc (b) 2nd field input cvbs href vs 313 314 315 316 317 318 319 320 321 69 x 2/llc handbook, full pagewidth (a) 1st field meh225-1 input cvbs href vs 525123456789 449x 2/llc (b) 2nd field input cvbs href vs 263 264 265 266 267 268 269 270 271 59 x 2/llc odd odd 2 x 2/llc 2 x 2/llc 60 hz 50 hz
may 1993 23 philips semiconductors preliminary speci?cation digital video scaler SAA7186 9i 2 c-bus format note 1. if more than 1 byte data are transmitted, then auto-increment of the subaddress is performed. s slave address a subaddress a data0 a datan a p s = start condition slave address = 1011 100x (iicsa = low) or 1011 110x (iicsa = high) a = acknowledge, generated by the slave subaddress (1) = subaddress byte (table 4) data = data byte (table 4) p = stop condition x = read/write control bit x = 0, order to write (the circuit is slave receiver) x = 1, order to read (the circuit is slave transmitter)
may 1993 24 philips semiconductors preliminary speci?cation digital video scaler SAA7186 table 4 i 2 c-bus; subaddress and data bytes for writing (x in address byte = 0). notes 1. default register contents fill in by hand 2. byte 10 is set to 00h after power-on reset. function subaddress data d7 d6 d5 d4 d3 d2 d1 d0 df (1) formats and sequence 00 rtb of1 of0 vpe lw1 lw0 fs1 fs0 tbf output data pixel/line 01 xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 continued in 04 xd9 xd8 input data pixel/line 02 xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 continued in 04 xs9 xs8 horizontal window start 03 xo7 xo6 xo5 xo4 xo3 xo2 xo1 xo0 pixel decimation ?lter 04 hf2 hf1 hf0 xo8 xs9 xs8 xd9 xd8 output data lines/?eld 05 yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 continued in 09 yd9 yd8 input data lines/?eld 06 ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 continued in 09 ys9 ys8 vertical window start 07 yo7 yo6 yo5 yo4 yo3 yo2 yo1 yo0 afs/vertical processing 08 afs vp1 vp0 yo8 ys9 ys8 yd9 yd8 vertical bypass start 09 vs7 vs6 vs5 vs4 vs3 vs2 vs1 vs0 continued in 0b vs8 vertical bypass count 0a vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 continued in 0b tcc 0 0 vs8 0 vc8 0 poe chroma keying lower limit for v upper limit for v lower limit for u upper limit for u 0c 0d 0e 0f vl7 vu7 ul7 uu7 vl6 vu6 ul6 uu6 vl5 vu5 ul5 uu5 vl4 vu4 ul4 uu4 vl3 vu3 ul3 uu3 vl2 vu2 ul2 uu2 vl1 vu1 ul1 uu1 vl0 vu0 ul0 uu0 byte 10 (2) 10 0 0 0 mct qpl qpp ttr efe unused 11 to 1f
may 1993 25 philips semiconductors preliminary speci?cation digital video scaler SAA7186 table 5 i 2 c-bus status byte (x in address byte = 1) function data d7 d6 d5 d4 d3 d2 d1 d0 status byte id3 id2 id1 id0 0 0 oef svp function of status bits: id3 to id0 software version of SAA7186 compatible with id3 id2 id1 id0 version 00 0 1 1 oef identi?cation of ?eld sequence dependent on inputs href and vs: 0 = even ?eld detected; 1 = odd ?eld detected svp state of vram port: 0 = inputs hfl and incadr inactive; 1 = inputs hfl and incadr active.
may 1993 26 philips semiconductors preliminary speci?cation digital video scaler SAA7186 table 6 function of the register bits of table 4 00 rtb rom table bypass switch: 0 = anti-gamma rom active 1 = table is bypassed -------------- ------------------------------------------------ of1 to of0 set output ?eld mode: of1 of0 ?eld mode dvs process 0 0 1 1 0 1 0 1 both ?elds for interlaced storage both ?elds for non-interlaced storage odd ?elds only (even ?elds ignored) for non-interlaced storage even ?elds only (odd ?elds ignored) for non-interlaced storage -------------- -------------------------------------------------- vpe vram port outputs enable: 0 = hfl and incadr inactive; vro outputs in 3-state position (hfl = low, incadr = high) 1 = hfl and incadr enabled; vro outputs dependent on voen -------------- ------------------------------------------------ lw1 to lw0 first pixel position in vro data for fs1 = 0; fs0 = 0 (rgb) and fs1 = 0; fs0 = 1 (yuv): lw1 lw0 31 to 24 23 to 16 15 to 8 7 to 0 0 0 1 1 0 1 0 1 pixel 0 pixel 0 black black pixel 0 pixel 0 black black pixel 1 pixel 1 pixel 0 pixel 0 pixel 1 pixel 1 pixel 0 pixel 0 ) ) ) ) efe = 0, trr = 0 first pixel position in vro data for fs1 = 1; fs0 = 1 (monochrome): lw1 lw0 31 to 24 23 to 16 15 to 8 7 to 0 0 0 1 1 0 1 0 1 pixel 0 black black black pixel 1 pixel 0 black black pixel 2 pixel 1 pixel 0 black pixel 3 pixel 2 pixel 1 pixel 0 ) ) ) ) efe = 0, trr = 0 0 0 1 1 0 1 0 1 pixel 0 black pixel 0 black pixel 1 pixel 0 pixel 1 pixel 0 x x x x x x x x ) ) ) ) efe = 1, trr = 0; lw only effects greyscale format
may 1993 27 philips semiconductors preliminary speci?cation digital video scaler SAA7186 fs1 to fs0 fifo output register format select (efe-bit see 10): efe fs1 fs0 output format (tables 2 and 3) 0 0 0 rgb 5-5-5 + alpa; 2 16-bit/pixel; 32-bit word length; rgb matrix on, vram output format 0 0 1 yuv 4:2:2; 2 16-bit/pixel; 32-bit word length; rgb matrix off, vram output format 0 1 0 yuv 4:2:2; video test mode; 1 16-bit/pixel; 16-bit word length; rgb matrix off, optional output format 0 1 1 monochrome mode; 4 8-bit/pixel; 32-bit word length; rgb matrix off, vram output format 1 0 0 rgb 5-5-5 + alpa; 1 16-bit/pixel; 16-bit word length; rgb matrix on, vram output + transparent format 1 0 1 yuv 4:2:2 + alpa; 1 16-bit/pixel; 16-bit word length; rgb matrix off, vram output + transparent format 1 1 0 rgb 8-8-8 + alpa; 1 24-bit/pixel; 24-bit word length; rgb matrix on, vram output + transparent format 1 1 1 monochrome mode; 2 8-bit/pixel; 16-bit word length; rgb matrix off, vram output + transparent format 01 and 04 xd9 to xd0 pixel number per line (straight binary) on output (vro): 00 0000 0000 to 11 1111 1111 (number of xs pixels as a maximum) 02 and 04 xs9 to xs0 pixel number per line (straight binary) on inputs (yin and uvin): 00 0000 0000 to 11 1111 1111 (number of input pixels per line as maximum) 03 and 04 xo8 to xo0 horizontal start position (straight binary) of scaling window (take care of active pixel number per line). start with 1st pixel after href rise = 0 0001 0000 to 1 1111 1111 (010 to 1ff) window start and window end may be cut by internal delay compensated href = 0 phase. xo has to be matched to the internal processing delay to get full scaling range
may 1993 28 philips semiconductors preliminary speci?cation digital video scaler SAA7186 04 hf2 to hf0 horizontal decimation ?lter (figures 13 and 14): hf2 hf1 hf0 taps ?lter 0 0 0 0 0 0 1 1 0 1 0 1 2 3 5 9 ?lter 1 (1/2 (1 + z - 1 )) ?lter 2 (1/4 (1 + 2z - 1 + z - 2 )) ?lter 3 (1/8 (1 + 2z - 1 + 2z - 2 + 2z - 3 + z - 4 )) ?lter 4 (1/16 (1 + 2z - 1 + 2z - 2 + 2z - 3 + 2z - 4 + 2z - 5 + 2z - 6 + 2z - 7 + z - 8 )) 1 1 1 0 0 1 0 1 0 1 1 8 ?lter bypassed ?lter bypassed + delay in y channel of 1t ?lter 5 (1/16 (1 + 3z - 1 + 3z - 2 + z - 3 + z - 4 + 3z - 5 + 3z - 6 + z - 7 )) 1 1 1 4 (1/8 (1 + 3z - 1 + 3z - 2 + z - 3 )) 05 and 08 yd9 to yd0 line number per output ?eld (straight binary): 00 0000 0000 to 11 1111 1111 (number of ys lines as a maximum) 06 and 08 ys9 to ys0 line number per input ?eld (straight binary): 00 0000 0000 11 1111 1111 0 line 1023 lines (maximum = number of lines/?eld - 3) 07 and 08 yo8 to yo0 vertical start of scaling window. 0 equals 3rd line after rising slope of vs input signal. take care of active line number per ?eld (straight binary). 0 0000 0000 start with 3rd line after the rising slope of vs 0 0000 0011 start with 1st line after the falling slope of nominal vs (saa7151b/91b) 1 1111 1111 511 + 3 lines after the rising slope of vs (maximum value) 08 afs adaptive ?lter switch: 0 = off; use vp1, vp0 and hf2 to hf0 bits 1 = on; ?lter characteristics are selected by the scaler -------------- ------------------------------------------- vp1 to vp0 vertical data processing vp1 vp0 processing 0 0 1 1 0 1 0 1 bypassed delay of one line h(z) = z - h vertical ?lter 1: (h(z) = 1/2 (1 + z - h )) vertical ?lter 2: (h(z) = 1/4 (1 + 2z - h + z - 2h )) 09 and 0b vs8 to vs0 vertical bypass start, sets begin of the bypass region (straight binary). scaling region overrides bypass region (yo bits): 0 0000 0000 start with 3rd line after the rising slope of vs 0 0000 0011 start with 1st line after the falling slope of nominal vs (saa7151b/91b) 1 1111 1111 511 + 3 lines after the rising slope of vs (maximum value)
may 1993 29 philips semiconductors preliminary speci?cation digital video scaler SAA7186 0a and 0b vc8 to vc0 vertical bypass count, sets length of bypass region (straight binary): 00 0000 0000 0 line length 11 1111 1111 511 lines length (maximum = number of lines/?eld - 3) -------------- ------------------------------------------------ tcc twos complement input data select (u, v): 0 = binary input data 1 = twos complement input data -------------- ----------------------------------------------- poe polarity, internally detected odd/even ?ag o/e: 0 = ?ag unchanged; 1 = ?ag inverted 0c vl7 to vl0 set lower limit for v colour-difference signal (8 bit; twos complement): 1000 0000 0000 0000 0111 1111 as maximum negative value = - 128 signal level limit = 0 as maximum positive value = +127 signal level 0d vu7 to vu0 set upper limit for v colour-difference signal (8 bit; twos complement): 1000 0000 0000 0000 0111 1111 as maximum negative value = - 128 signal level limit = 0 as maximum positive value = +127 signal level 0e ul7 to ul0 set lower limit for u colour-difference signal (8 bit; twos complement): 1000 0000 0000 0000 0111 1111 as maximum negative value = - 128 signal level limit = 0 as maximum positive value = +127 signal level 0f uu7 to uu0 set upper limit for u colour-difference signal (8 bit; twos complement): 1000 0000 0000 0000 0111 1111 as maximum negative value = - 128 signal level limit = 0 as maximum positive value = +127 signal level
may 1993 30 philips semiconductors preliminary speci?cation digital video scaler SAA7186 10 mct monochrome and twos complement output data select: 0 = inverse greyscale luminance (if greyscale is selected by fs bits) or straight binary u, v data output 1 = non-inverse monochrome luminance (if greyscale is selected by fs bits) or twos complement u, v data output -------------- ------------------------------------------------ qpl line quali?er polarity ?ag : 0 = lnq is active-low (pin 1 and on vro1, pin 99); 1 = lnq is active-high -------------- ---------------------------------------------- qpp pixel quali?er polarity ?ag : 0 = pxq is active-low (vro0, pin 100); 1 = pxq is active-high -------------- ------------------------------------------------ ttr transparent data transfer: 0 = normal operation (vram protocol valid,) 1 = fifo register transparent (output fifo in shift register mode) -------------- ------------------------------------------------ efe extended formats enable, fs-bits in subaddress 00
may 1993 31 philips semiconductors preliminary speci?cation digital video scaler SAA7186 fig.13 horizontal frequency characteristic of luminance signal (y) dependent on hf2 to hf0 bits (subaddress 04). handbook, full pagewidth 0.5 10 - 50 0 0.1 0.2 100, 101 000 001 111 011 011 110 010 110 0.3 0.4 - 10 0 - 40 - 30 - 20 meh514 f / f clock (db) handbook, full pagewidth 0.25 10 - 50 0 f / f clock 011, 110 (db) 0.05 0.10 0.15 0.20 - 10 0 - 40 - 30 - 20 meh513 010 001 000 111 011, 110 100, 101 fig.14 horizontal frequency characteristic of chrominance signals (uv) without uv interpolation dependent on hf2 to hf0 bits (subaddress 04).
may 1993 32 philips semiconductors preliminary speci?cation digital video scaler SAA7186 10 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. 11 dc characteristics v dd1 to v dd8 = 4.5 to 5.5 v; t amb = 0 to 70 c unless otherwise speci?ed. symbol parameter min. max. unit v dd supply voltage (pins 5, 14, 26, 40, 55, 67, 76 and 91) - 0.5 6.5 v v i dc input voltage on all pins - 0.5 v dd v i dd supply current (pins 5, 14, 26, 40, 55, 67, 76 and 91) - 70 ma p tot total power dissipation 0 1 w t stg storage temperature range - 65 150 c t amb operating ambient temperature range 0 70 c v esd electrostatic handling (1) for all pins - 2000 v symbol parameter conditions min. typ. max. unit v dd supply voltage range (pins 5, 14, 26, 40, 55, 67, 76 and 91) 4.5 5 5.5 v i p total supply current (i dd1 + i dd2 + i dd3 + i dd4 + i dd5 + i dd6 + i dd7 + i dd8 ) inputs low and outputs without load - 80 - ma data and control inputs v i l input voltage low - 0.5 - 0.8 v v i h input voltage high 2.0 - v dd + 0.5 v i li input leakage current v i l =0 -- 10 m a c i input capacitance data -- 8pf clocks -- 10 pf data and control outputs v o l output voltage low note 1 -- 0.6 v v o h output voltage high note 1 2.4 -- v 3-state outputs i o off high-impedance output current -- 5 m a c o high-impedance output capacitance -- 8pf i 2 c-bus, sda and scl (pins 44 and 45) v i l input voltage low - 0.5 - 1.5 v v i h input voltage high 3 - v dd + 0.5 v i 44, 45 input current -- 10 m a i ack output current on pin 44 acknowledge 3 -- ma v o l output voltage at acknowledge i 44 = 3 ma -- 0.4 v
may 1993 33 philips semiconductors preliminary speci?cation digital video scaler SAA7186 12 ac characteristics v dd1 to v dd8 = 4.5 to 5.5 v; t amb = 0 to 60 c unless otherwise speci?ed. notes 1. levels are measured with load circuit. vro outputs with 1.2 k w in parallel to 25 pf at 3 v (ttl load). 2. maximum t vclk = 200 ns for test mode only. the applicable maximum cycle time depends on data format, horizontal scaling and input data rate. 3. measured at 1,5 v level; t p l may be unlimited. 4. timings of vro refer to the rising edge of vlck. 5. the timing of incadr refers to llc; the rising edge of hfl always refers to llc. during a vram transfer is the falling edge of hfl generated by vclk. both edges of hfl refer to llc during horizontal increment and vertical reset cycles. 6. asynchronous signals with timing referring to the 1.5 v switching point of voen input signal (pin 50). symbol parameter conditions min. typ. max. unit llc timing (pin 36) fig.11 t llc cycle time 31 - 45 ns t p pulse width (duty factor) t llc h / t llc 40 50 60 % t r rise time -- 5ns t f fall time -- 6ns input data and cref timing fig.15 t su setup time 11 -- ns t hd hold time 3 -- ns vclk timing (pin 51) fig.16 t vclk vram port clock cycle time note 2 50 - 200 ns t p l , t p h low and high times note 3 17 -- ns t r rise time -- 5ns t f fall time -- 6ns output data and reference signal timing figures 15 and 16 c l load capacitance vro outputs 15 - 40 pf other outputs 7.5 - 25 pf t oh vro data hold time c l = 10 pf; note 4 0 -- ns t ohl related to llc (incadr, hfl) c l = 10 pf; note 5 0 - ns t ohv related to vclk (hfl) c l = 10 pf; note 5 0 - ns t od vro data delay time c l = 40 pf; note 4 -- 25 ns t odl related to llc (incadr, hfl) c l = 25 pf; note 5 -- 60 ns t odv related to vclk (hfl) c l = 25 pf; note 5 -- 60 ns t d output disable time to 3-state c l = 40 pf; note 6 -- 40 ns t e output enable time from 3-state c l = 40 pf; note 6 -- 40 ns t hfl voe hfl maximum response time vram port enabled -- 810 ns t hfl vclk hfl maximum response time hfl set at beginning of vclk burst -- 840 ns
may 1993 34 philips semiconductors preliminary speci?cation digital video scaler SAA7186 handbook, full pagewidth meh408-1 clock input llc t llc h t llc t f t r 2.4 v 1.5 v 0.6 v input data output hfl and incadr t su t hd t ohl 2.0 v 0.8 v 2.4 v 0.6 v t odl not valid not valid 2.0 v 0.8 v inputs cref t hd t su fig.15 data input timing (llc).
may 1993 35 philips semiconductors preliminary speci?cation digital video scaler SAA7186 13 processing delays ports delay in llc remarks yin to vro uvin to vro href to vro 58 58 58 in transparent mode only in transparent mode only in transparent mode only handbook, full pagewidth meh409 voen 2.0 v 1.5 v 0.8 v vclk output vro(n) 2.0 v 0.8 v 2.4 v 0.6 v not valid 0.6 v 2.4 v output hfl t f t r t vclk t p l t p h t en t od t oh t odv t ohv 1.5 v fig.16 data output timing (vclk).
may 1993 36 philips semiconductors preliminary speci?cation digital video scaler SAA7186 14 programming example slave address byte is b8h at pin iicsa = 0 (or bch at pin iicsa = +5 v). this example shows the setting via i 2 c-bus for the processing of a picture segment at 1:1 horizontal and vertical scale. values in brackets [..]: if no scaling or panning is wanted, the parameters xd, xs, yd and ys should be set to the maximum value 3ffh. the parameters xo and yo should be set to the minimum value 000h. (in this case, href and vs from external de?ne the SAA7186 processing window). notes 1. rtb = 0 rom table is active (only for rgb formats) of = 00 SAA7186 processes the both fields for interlaced display vpe = 1 vram port is enabled lw = 00 longword position of first pixel in each output line = 0 fs = 01 16-bit 4:2:2 yuv output format is selected 2. for nominal vs length of 6 h-period (input saa7191b respectively saa7151b with active vnl) 3. ttc = 0 straight binary uv input data expected subaddr. (hex) bits function value (hex) comment 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 rtb, of(1:0), vpe, lw(1:0), fs(1:0), xd(7:0) xs(7:0) xo(7:0) hf(2:0), xo(8), xs(9, 8), xd(9, 8) yd(7:0) ys(7:0) yo(7:0) afs, vp(1:0), yo(8), ys(9, 8), yd(9, 8) vs(7:0) vc(7:0) vs(8), vc(8), tcc, poe vl(7:0) vu(7:0) ul(7:0) uu(7:0) mct, qpp, qpl, ttr, efe rom table control and ?eld sequence processing; vram port enable; output format select lsbs output pixel/line lsbs input pixel/line lsbs for horizontal window start horizontal ?lter select and msbs of subaddresses 01, 02, 03 lsbs output lines/?eld lsbs input lines/?eld lsbs vertical window start adaptive and vertical ?lter select; msbs of subaddresses 05, 06, 07 lsbs vertical bypass start position lsbs vertical bypass lines/?eld msbs of subaddresses 09, 0a; uv input data representation and odd/even polarity switch uv keyer: lower limit v (r-y) uv keyer: upper limit v (r-y) uv keyer: lower limit u (b-y) uv keyer: upper limit u (b-y) y or uv output data representation, output data transfer mode, pixel/ line quali?er polarity. 11 80 [ff] 80 [ff] 10 [00] 85 [8f] 90 [ff] 90 [ff] 03 [00] 00 [ff] 00 00 00 00 ff 00 00 00 (1) 384 pixels out 384 pixels in 1st pixel after href = 1 horizontal ?lter bypassed 144 lines out 144 lines in 1st line after vs = 0; (2) no adaptive select vertical ?lter bypassed not bypassed region de?ned; (3) (4) ) keying is switched off ) by vu < vl - - (5)
may 1993 37 philips semiconductors preliminary speci?cation digital video scaler SAA7186 4. odd/even polarity unchanged - can be used to change the field sequence if phase relations between href and vs are not according to saa7191b respectively saa7151b specification 5. mct = 0 when efe, fs = 001h: uv output data are straight binary qpp = 0 the pixel qualifier pxq is 0-active (if ttr, efe = 1) qpl = 0 line qualifier lnq is 0-active (if ttr, efe = 1) ttr = 0 vram port is set to data burst transfer efe = 0 32-bit longword formats selected.
may 1993 38 philips semiconductors preliminary speci?cation digital video scaler SAA7186 15 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.40 0.25 0.25 0.14 14.1 13.9 0.65 18.2 17.6 1.4 1.2 1.0 0.6 7 0 o o 0.15 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot317-2 92-11-17 95-02-04 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 0.8 0.4 d e q e a 1 a l p q detail x l (a ) 3 b 30 c b p e h a 2 d z d a z e e v m a 1 100 81 80 51 50 31 pin 1 index x y b p d h v m b w m w m 0 5 10 mm scale qfp100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot317-2 a max. 3.20
may 1993 39 philips semiconductors preliminary speci?cation digital video scaler SAA7186 16 soldering 16.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 16.2 re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 16.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
may 1993 40 philips semiconductors preliminary speci?cation digital video scaler SAA7186 17 definitions 18 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 19 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
may 1993 41 philips semiconductors preliminary speci?cation digital video scaler SAA7186 notes
may 1993 42 philips semiconductors preliminary speci?cation digital video scaler SAA7186 notes
may 1993 43 philips semiconductors preliminary speci?cation digital video scaler SAA7186 notes
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